Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
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AbstractIn spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become suboptimal after going through physical design flow. Adder design has been such a long studied fundamental problem in very large-scale integration industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-the-art prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning-based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Considering the high cost of obtaining the true values for learning, an active learning algorithm is proposed to select the representative data during learning process, which uses less labeled data while achieving better quality of Pareto frontier. Experimental results demonstrate that our framework can achieve Pareto frontier of high quality over a wide design space, bridging the gap between architectural and physical designs. Source code and data are available at https://github.com/yuzhe630/adder-DSE .
All Author(s) ListYuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
Journal nameIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year2019
Month12
Volume Number38
Issue Number12
Pages2298 - 2311
ISSN0278-0070
eISSN1937-4151
LanguagesEnglish-United States

Last updated on 2020-21-10 at 02:49