A Fully Integrated Low-Dropout Regulator With Differentiator-Based Active Zero Compensation
Publication in refereed journal

香港中文大學研究人員
替代計量分析
.

其它資訊
摘要An area-efficient low-power fully integrated output-capacitorless low-dropout regulator (OCL-LDO) is presented in this paper. The three-stage OCL-LDO utilizes an embedded differentiator-based active zero compensation technique together with adaptive biasing. The proposed active zero compensation helps enhance the unity-gain bandwidth (UGB) of the regulator with very small silicon area and almost no extra current consumption. The UGB is therefore able to be maintained above 2.5 MHz even at a measured quiescent current of mere 1.6 μA. Adaptive bias is employed to further stabilize the circuit and extend the bandwidth extension as well as enhance the transient response. The chip area is 0.0021 mm 2 with maximum load capability of 25 mA, which leads to a maximum current density of 11.9 A/mm 2 . The measured voltage spikes are below 40 mV for full-load transient responses, and the response time is about 1.2 ns. The voltage spikes of line transient responses are only 4 mV at full load. The measured full-load power-supply rejection is better than -44 dB up to 100 kHz.
著者Bu S, Leung KN, Lu Y, Guo JP, Zheng YQ
期刊名稱IEEE Transactions on Circuits and Systems I: Regular Papers
出版年份2018
月份10
卷號65
期次10
出版社IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
頁次3578 - 3591
國際標準期刊號1549-8328
電子國際標準期刊號1558-0806
語言英式英語
關鍵詞Low-dropout regulator, current density, area-efficient, power management, frequency compensation, Miller compensation
Web of Science 學科類別Engineering, Electrical & Electronic;Engineering

上次更新時間 2020-02-06 於 01:15