Active-RC continuous-time DSM with FIR+SCR DAC
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
替代計量分析
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其它資訊
摘要This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv..
著者Yang Zhang, Debajit Basak, Daxiang Li, Kong-Pang Pun
會議名稱13th IEEE International Conference on Electron Devices and Solid-State Circuits
會議開始日18.10.2017
會議完結日20.10.2017
會議地點Hsinchu
會議國家/地區台灣
會議論文集題名IEEE International Conference on Electron Devices and Solid-State Circuits
出版年份2017
頁次1 - 2
國際標準書號978-153862907-9
語言英式英語
關鍵詞Continuous-time Delta-Sigma modulator, FIR and switched-capacitor DAC

上次更新時間 2020-17-11 於 01:38