Active-RC continuous-time DSM with FIR+SCR DAC
Refereed conference paper presented and published in conference proceedings


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AbstractThis paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv..
All Author(s) ListYang Zhang, Debajit Basak, Daxiang Li, Kong-Pang Pun
Name of Conference13th IEEE International Conference on Electron Devices and Solid-State Circuits
Start Date of Conference18/10/2017
End Date of Conference20/10/2017
Place of ConferenceHsinchu
Country/Region of ConferenceTaiwan
Proceedings TitleIEEE International Conference on Electron Devices and Solid-State Circuits
Year2017
Pages1 - 2
ISBN978-153862907-9
LanguagesEnglish-United Kingdom
KeywordsContinuous-time Delta-Sigma modulator, FIR and switched-capacitor DAC

Last updated on 2020-04-07 at 03:12