Reduction of clock jitter effect in 1-bit CT delta-sigma modulators by correlated clocks
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
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摘要A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis shows that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
著者Yang Zhang, Daxiang Li, Debajit Basak, Kong-Pang Pun
會議名稱13th IEEE International Conference on Electron Devices and Solid-State Circuits
會議開始日18.10.2017
會議完結日20.10.2017
會議地點Hsinchu, Taiwan
會議國家/地區台灣
會議論文集題名IEEE International Conference on Electron Devices and Solid-State Circuits
出版年份2017
頁次1 - 2
國際標準書號978-1-5386-2907-9
語言英式英語
關鍵詞Clock jitter reduction, continuous-time Delta Sigma modulator

上次更新時間 2020-21-11 於 02:36