Acceleration of a physically derived micro-modeling circuit for packaging problems using graphics processing units
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
替代計量分析
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其它資訊
摘要The physically derived micro-modeling circuit is an order-reduced RLC circuit of a PEEC circuit for a large-scale packaging problem. Unlike traditional model order reduction (MOR) methods, this method can reduce the order of the circuit by an order of magnitude without any matrix inversions and decompositions. As its dominant computation is outer products of a vector by itself, the scheme is highly suitable for parallel computation. This paper proposes an effective collaborative acceleration strategy for deriving a micro-modeling circuit using a GPU module. The strategy combines an efficient parallel computation of a vector outer products using GPU and an I/O optimization for data transfer between CPU and GPU. A numerical example shows that the proposed acceleration method by parallel computation for deriving the micro-modeling circuit is nearly proportional to the number of computing cores. It is demonstrated that the micro-modeling scheme is highly suitable for a large-scale interconnection and packaging problem.
出版社接受日期24.12.2016
著者Yuhang Dou, Ke-Li Wu
會議名稱2017 IEEE MTT-S International Microwave Symposium
會議開始日04.06.2017
會議完結日09.06.2017
會議地點Honolulu
會議國家/地區美國
會議論文集題名2017 IEEE MTT-S International Microwave Symposium (IMS)
出版年份2017
月份6
國際標準書號978-1-5090-6361-1
電子國際標準書號978-1-5090-6360-4
語言美式英語

上次更新時間 2020-28-11 於 00:12