Acceleration of a physically derived micro-modeling circuit for packaging problems using graphics processing units
Refereed conference paper presented and published in conference proceedings

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AbstractThe physically derived micro-modeling circuit is an order-reduced RLC circuit of a PEEC circuit for a large-scale packaging problem. Unlike traditional model order reduction (MOR) methods, this method can reduce the order of the circuit by an order of magnitude without any matrix inversions and decompositions. As its dominant computation is outer products of a vector by itself, the scheme is highly suitable for parallel computation. This paper proposes an effective collaborative acceleration strategy for deriving a micro-modeling circuit using a GPU module. The strategy combines an efficient parallel computation of a vector outer products using GPU and an I/O optimization for data transfer between CPU and GPU. A numerical example shows that the proposed acceleration method by parallel computation for deriving the micro-modeling circuit is nearly proportional to the number of computing cores. It is demonstrated that the micro-modeling scheme is highly suitable for a large-scale interconnection and packaging problem.
Acceptance Date24/12/2016
All Author(s) ListYuhang Dou, Ke-Li Wu
Name of Conference2017 IEEE MTT-S International Microwave Symposium
Start Date of Conference04/06/2017
End Date of Conference09/06/2017
Place of ConferenceHonolulu
Country/Region of ConferenceUnited States of America
Proceedings Title2017 IEEE MTT-S International Microwave Symposium (IMS)
Year2017
Month6
ISBN978-1-5090-6361-1
eISBN978-1-5090-6360-4
LanguagesEnglish-United States

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