An 11b 40MS/s charge pump and comparator based pipelined ADC with variable reset voltages
Refereed conference paper presented and published in conference proceedings

Altmetrics Information
.

Other information
AbstractThis paper presents a power-efficient pipelined analog-to-digital converter targeted for applications in 4G-LTE mobile terminals. A charge pump and comparator based circuit realizes the proposed residue voltage amplification with variable reset voltages to save power. The performance of the amplification technique has been verified through simulations using a standard 0.18-μm CMOS process. It achieves 62.9-dB SNDR at 40MS/s sampling rate and consumes 5.8-mW power under a 1.8-V supply, resulting in an ENOB of 1.2 pJ/conv.-step.
All Author(s) ListDaxiang Li, Xian Tang, Zhongyi Fu, Jiangpeng Wang, Debajit Basak, Kong-Pang Pun
Name of Conference2016 IEEE International Conference on Electron Devices and Solid-State Circuits
Start Date of Conference03/08/2016
End Date of Conference05/08/2016
Place of ConferenceHong Kong
Country/Region of ConferenceHong Kong
Proceedings TitleProceedings of 2016 IEEE International Conference on Electron Devices and Solid-State Circuits
Year2016
PublisherIEEE
Pages383 - 386
ISBN978-1-5090-1831-4
eISBN978-1-5090-1830-7
LanguagesEnglish-United States
Keywordscharge pump, residue amplification, foreground calibration, pipelined ADC

Last updated on 2021-15-01 at 00:17