An FPGA-Friendly Algorithm for QR Code Detection
Refereed conference paper presented and published in conference proceedings


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AbstractQR code is widely used in different applications, and its detection is currently being done by software. However, hardware detection using FPGAs offers real-time processing ability, which makes it attractive for time-critical applications, such as high-precision robotics and augmented reality. In light of this, an FPGA algorithm for QR code detection is proposed in this paper. It operates with a maximum latency of 12.2 ms to detect a QR code when the input image resolution is 640 × 480, which offers a 85.3% performance boost over the best state-of-the-art software detector according to benchmarks. To the best of the authors' knowledge, this is the first work that explores the use of FPGA in QR code detection.
All Author(s) ListLam K.K.L., Sum K.W.
Name of ConferenceIEEE International Symposium on Circuits and Systems
Start Date of Conference21/05/2023
End Date of Conference25/05/2023
Place of ConferenceMonterey, California
Country/Region of ConferenceUnited States of America
Proceedings TitleIEEE International Symposium on Circuits and Systems (ISCAS)
Year2023
Month5
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN9781665451093
LanguagesEnglish-United Kingdom
KeywordsFPGA, machine vision, QR code, real-time

Last updated on 2024-16-04 at 00:35