Design of self-timed asynchronous booth's multiplier
Refereed conference paper presented and published in conference proceedings

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AbstractThis paper presents a design of multiplier for the multiplication of two 8-bit two-complement numbers. The multiplier applies the self-timed asynchronous methodology such that the multiplier can be assumed to operate on average case delay. And also, modified booth's algorithm [1] is used to reduce the number of partial product generated. As a result, the speed of the multiplier can be improved. © 2000 IEEE.
All Author(s) ListTang T.-Y., Choy C.-S., Siu P.-L., Chan C.-F.
Name of Conference2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Start Date of Conference25/01/2000
End Date of Conference28/01/2000
Place of ConferenceYokohama
Country/Region of ConferenceJapan
Pages15 - 16
LanguagesEnglish-United Kingdom

Last updated on 2021-11-09 at 23:45