Design of self-timed asynchronous booth's multiplier
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
替代計量分析
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摘要This paper presents a design of multiplier for the multiplication of two 8-bit two-complement numbers. The multiplier applies the self-timed asynchronous methodology such that the multiplier can be assumed to operate on average case delay. And also, modified booth's algorithm [1] is used to reduce the number of partial product generated. As a result, the speed of the multiplier can be improved. © 2000 IEEE.
著者Tang T.-Y., Choy C.-S., Siu P.-L., Chan C.-F.
會議名稱2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
會議開始日25.01.2000
會議完結日28.01.2000
會議地點Yokohama
會議國家/地區日本
出版年份2000
月份12
日期1
頁次15 - 16
國際標準書號0780359747
語言英式英語

上次更新時間 2021-16-10 於 23:35