VLSI architecture for digital-recurrence algorithms on divider
Refereed conference paper presented and published in conference proceedings


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AbstractThe digital recurrence algorithms based on redundant quotient-digit set and prediction of result-digits have significant speed and cost advantages. Here we propose a VLSI implementation architecture which uses a register free domino structure to reduce the number of gates, as well as to make the circuit work at high speed. The results circuit in 0.6 um CMOS technology has a area of 1.8mm × 1.9mm and the evaluation time for 8-bit quotient-digit generation is about 13ns.
All Author(s) ListYang Jing-ling, Choy Chiu-sing, Chan Cheong-fat
Name of ConferenceCCECE 2000-Canadian Conference on Electrical and Computer Egineering
Start Date of Conference07/05/2000
End Date of Conference10/05/2000
Place of ConferenceNova Scotia, NS, Can
Country/Region of ConferenceCanada
Detailed descriptionPaper presented in CCECE 2000, organized by IEEE.
Year2000
Month12
Day3
Volume Number1
Pages403 - 406
ISSN0840-7789
LanguagesEnglish-United Kingdom

Last updated on 2020-03-09 at 02:03