ForTER: A forward error correction scheme for timing error resilience
Refereed conference paper presented and published in conference proceedings

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AbstractWith technology scaling, integrated circuits suffer from increasingly severe static and dynamic variations, which often manifest themselves as infrequent timing errors on circuit speed paths, if a large timing guard-band is not reserved. This paper presents a new forward timing error correction scheme, namely ForTER, which predicts whether the occurrence of timing errors would propagate to the next level of sequential elements and corrects them without necessarily borrowing timing slack. The proposed technique can be combined with other timing error resilient circuit design techniques to further improve circuit performance, as demonstrated in our experimental results with various benchmark circuits. © 2013 IEEE.
All Author(s) ListZhang J., Yuan F., Ye R., Xu Q.
Name of Conference2013 32nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013
Start Date of Conference18/11/2013
End Date of Conference21/11/2013
Place of ConferenceSan Jose, CA
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by IEEE/ACM,
Pages55 - 60
LanguagesEnglish-United Kingdom

Last updated on 2020-14-10 at 02:23