3-D floorplanning using labeled tree and dual sequences
Refereed conference paper presented and published in conference proceedings

替代計量分析
.

其它資訊
摘要3-D packing is an NP-hard problem with wide applications in microelectronic circuit design such as 3-D packaging, 3-D VLSI placement and dynamically reconfigurable FGPA design. We present a complete representation for general non-slicing 3-D floorplan or packing structures, which uses a labeled tree and dual sequences. For each compact placement, there is a corresponding encoding. The number of possible tree-sequence combinations is (n + 1)n-1(n!) 2, the lowest among complete 3-D representations up to date. The construction of placement from an encoding needs O(n2) in the worst case, but in practical cases we expect O(n4/3 log n) time on average for circuit blocks with limited length/width ratios. Experimental results show promising performance using the labeled tree and dual sequences on 3-D floorplan and placement optimizations. Copyright 2008 ACM.
著者Wang R., Young E.F.Y., Znu Y., Graham F.C., Graham R., Cheng C.-K.
會議名稱2008 ACM International Symposium on Physical Design, ISPD 2008
會議開始日13.04.2008
會議完結日16.04.2008
會議地點Portland, OR
會議國家/地區美國
詳細描述organized by ACM,
出版年份2008
月份5
日期16
頁次54 - 59
國際標準書號9781605580487
語言英式英語
關鍵詞3-D packing, Labeled tree, Sequence

上次更新時間 2021-13-06 於 00:21