Analog and Digital FPGA Implementation of BRIN for Optimization Problems
Publication in refereed journal

CUHK Authors
Author(s) no longer affiliated with CUHK

Times Cited
Altmetrics Information

Other information
AbstractThe binary relation inference network (BRIN) shows promise in obtaining the global optimal solution for optimization problem, which is time independent of the problem size. However, the realization of this method is dependent on the implementation platforms. In this paper, we studied analog and digital FPGA implementation platforms. Analog implementation of BRIN for two different directed graph problems is studied. As transitive closure problems can transform to a special case of shortest path problems or a special case of maximum spanning tree problems, two different forms of BRIN are discussed. Their circuits using common analog integrated circuits are investigated. The BRIN solution for critical path problems is expressed and is implemented using the separated building block circuit and the combined building block circuit. As these circuits are different, the response time of these networks will be different. The advancement of field programmable gate arrays (FPGAs) in recent years, allowing millions of gates on a single chip and accompanying with high-level design tools, has allowed the implementation of very complex networks. With this exemption on manual circuit construction and availability of efficient design platform, the BRIN architecture could be built in a much more efficient way. Problems on bandwidth are removed by taking all previous external connections to the inside of the chip. By transforming BRIN to FPGA (Xilinx XC4010XL and XCV800 Virtex), we implement a synchronous network with computations in a finite number of steps. Two case studies are presented, with correct results verified from simulation implementation. Resource consumption on FPGAs is studied showing that Virtex devices are more suitable for the expansion of network in future developments.
All Author(s) ListNg H.S., Lam K.P.
Journal nameIEEE Transactions on Neural Networks
Volume Number14
Issue Number5
PublisherInstitute of Electrical and Electronics Engineers
Place of PublicationUnited States
Pages1413 - 1425
LanguagesEnglish-United Kingdom
KeywordsAnalog circuit, Connectionist network, Field programmable gate array (FPGA), Optimization problems, Xilinx XC4010XL

Last updated on 2020-10-08 at 00:48