A 25-kHz 3rd-order continuous-time Delta-Sigma modulator using tri-level quantizer
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
替代計量分析
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其它資訊
摘要This paper presents a 3rd order continuous-time Delta-Sigma modulator with a tri-level quantizer, which provides 3-dB reduction of quantization noise without dynamic element matching (DEM). The tri-level DAC linearity is analyzed and it shows that a highly linear tri-level DAC can be realized in fully-differential active-RC Delta-Sigma modulator. The performance of the tri-level continuous-time Delta-Sigma modulator has been verified through simulations using a standard 0.18-μm CMOS process. It achieves 81-dB SNDR at 3.2-MS/s sampling rate and consumes 1.14-μW power with ideal amplifier.
著者Li D., Pun K.-P.
會議名稱5th International Symposium on Next-Generation Electronics, ISNE 2016
會議開始日04.05.2016
會議完結日06.05.2016
會議地點Hsinchu
會議國家/地區台灣
詳細描述organized by National Tsing Hua University, Hsinchu, Taiwan,
出版年份2016
月份8
日期12
國際標準書號9781509024391
語言英式英語

上次更新時間 2021-15-01 於 00:02