A 10-bit 2 MS/s SAR ADC using reverse VCM-based switching scheme
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AbstractThis paper presents a successive-approximation-register (SAR) analogue-to-digital converter (ADC) using a tri-level switching scheme named as reverse VCM-based scheme which maintains good linearity without any driving and accuracy requirements on VCM. A 10-bit SAR ADC is designed in a 0.18 CMOS technology. With a unit capacitor size of 17.2 fF, the ADC consumes 41.9 μW from a 1.8 V voltage supply. The measured signal-to-noise-plus-distortion ratio (SNDR) is 59.6 dB at 2 MS/s. The figure-of-merit (FOM) is 26.9 fJ/conv.-step.
All Author(s) ListFu Z., Tang X., Li D., Wang J., Basak D., Pun K.-P.
Name of Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Start Date of Conference22/05/2016
End Date of Conference25/05/2016
Place of ConferenceMontreal
Country/Region of ConferenceCanada
Detailed descriptionorganized by IEEE Circuits and Systems Society,
Volume Number2016-July
Pages1030 - 1033
LanguagesEnglish-United Kingdom

Last updated on 2021-13-04 at 23:27