A 1.9 μW transient-enhanced low-dropout regulator with voltage-spike suppression
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
替代計量分析
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摘要A low-voltage low-dropout regulator (LDO) with voltage-spike suppression is presented in this paper. The proposed LDO is formed by multiple gain stages to improve the loop gain and loop bandwidth simultaneously. The LDO is compensated by a zero generated by the equivalent series resistance (ESR) of the output capacitor, as well as a zero created by the high-pass feedback network. Moreover, the structure contains a capacitive-coupling push-pull stage controlled by a voltage comparator to improve slew rate at the gate of the power transistor in order to suppress the output voltage spike without increasing the bias current. The proposed LDO is implemented by a 0.35-μm CMOS technology (VTHN ≈ 0.5 V and VTHP ≈ -0.65 V). The active area of the chip is 310 μm × 1010 μm. The minimum operating input voltage is 1 V and the preset output voltage is 0.9 V, with quiescent current of 1.9 μA. Measured maximum output current is 91 mA. Load transient measurement shows the voltage spike can be completely suppressed. Copyright © 2010 American Scientific Publishers All rights reserved.
著者Leung K.N., Cheung F.K.M., Ho M., Poon H.C., Or P.Y.
出版年份2010
月份4
日期1
卷號6
期次1
出版社American Scientific Publishers
出版地United States
頁次126 - 132
國際標準期刊號1546-1998
語言英式英語
關鍵詞Low-Dropout Regulator, Power Management, Voltage Spike

上次更新時間 2020-29-11 於 01:43