A dual-MST approach for clock network synthesis
Refereed conference paper presented and published in conference proceedings

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AbstractIn nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Voltage and Temperature) variations contribute a lot to its behavior. Previous worksmainly focused on skew and wirelengthminimization. It may lead to negative influence towards these process variation factors. In this paper, a novel clock network synthesizer is proposed and several algorithms are introduced for performance improvement. A dual-MST (DMST) geometric matching approach is proposed for topology construction. It can help balancing the tree structure to reduce the variation effect. A recursive buffer insertion technique and a blockage handlingmethod are also presented, and they are developed for proper distribution of buffers and saving of capacitance. Experimental results show that our matching approach is better than the traditional methods, and in particular our synthesizer has better performance compared to the results of the winner in the ISPD 2009 contest.
All Author(s) ListLu J., Chow W.-K., Sham C.-W., Young E.F.Y.
Name of Conference2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Start Date of Conference18/01/2010
End Date of Conference21/01/2010
Place of ConferenceTaipei
Country/Region of ConferenceTaiwan
Detailed descriptionorganized by IEEE,
Pages467 - 473
LanguagesEnglish-United Kingdom

Last updated on 2021-16-09 at 00:16