A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages
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AbstractA two-stage large-capacitive-load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain-bandwidth product (GBW). Implemented in a standard 0.13-μm CMOS technology and powered by a 0.7 V supply with a current consumption of 20 μA, the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a capacitive load of 9.5 nF. The average slew rate is 0.3679 V/μs. The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.
All Author(s) ListHo M., Guo J., Mui T.W., Mak K.H., Goh W.L., Poon H.C., Bu S., Lau M.W., Leung K.N.
Journal nameIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume Number24
Issue Number7
PublisherInstitute of Electrical and Electronics Engineers
Place of PublicationUnited States
Pages2580 - 2592
LanguagesEnglish-United Kingdom
KeywordsMiller compensation, slew rate (SR), small-gain stages, two-stage amplifier

Last updated on 2021-30-11 at 23:44