On logic synthesis for timing speculation
Refereed conference paper presented and published in conference proceedings


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摘要By allowing the occurrence of infrequent timing errors and correcting them with rollback mechanisms, the so-called timing speculation (TS) technique can significantly improve circuit energy-efficiency and hence has become one of the most promising solutions to mitigate the ever-increasing variation effects in nanometer technologies. As timing error recovery incurs non-trivial performance/energy overhead, it is important to reshape the delay distribution of critical paths in timing-speculated circuits to minimize their timing error rates. Most existing TS optimization techniques achieve this objective with post-synthesis techniques such as gate sizing or body biasing. In this work, we propose to conduct logic synthesis for timing-speculated circuits from the ground up. Being able to manipulate circuit structures during logic optimization, the proposed solution is able to dramatically reduce circuit timing error rates and hence improve its throughput, as demonstrated with experimental results on various benchmark circuits. © 2012 ACM.
著者Liu Y., Ye R., Yuan F., Kumar R., Xu Q.
會議名稱2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012
會議開始日05.11.2012
會議完結日08.11.2012
會議地點San Jose, CA
會議國家/地區美國
出版年份2012
月份12
日期1
頁次591 - 596
國際標準期刊號1092-3152
語言英式英語

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