Modeling TSV open defects in 3D-stacked DRAM
Refereed conference paper presented and published in conference proceedings

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AbstractThree-dimensional (3D) stacking using through silicon vias (TSVs) is a promising solution to provide low-latency and high-bandwidth DRAM access from microprocessors. The large number of TSVs implemented in 3D DRAM circuits, however, are prone to open defects and coupling noises, leading to new test challenges. Through extensive simulation studies, this paper models the faulty behavior of TSV open defects occurred on the wordlines and the bitlines of 3D DRAM circuits, which serves as the first step for efficient and effective test and diagnosis solutions for such defects. © 2010 IEEE.
All Author(s) ListJiang L., Liu Y., Duan L., Xie Y., Xu Q.
Name of Conference41st International Test Conference, ITC 2010
Start Date of Conference31/10/2010
End Date of Conference05/11/2010
Place of ConferenceAustin, TX
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by IEEE,
LanguagesEnglish-United Kingdom

Last updated on 2021-18-02 at 23:48