On signal tracing for debugging speedpath-related electrical errors in post-silicon validation
Refereed conference paper presented and published in conference proceedings

Times Cited
Altmetrics Information

Other information
AbstractOne of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speed-paths in the circuit under debug (CUD) and only expose themselves in a certain electrical environment. To address this problem, we propose a trace-based silicon debug solution, which provides real-time visibility to the speedpaths in the CUD during normal operation. Since tracing all speedpath-related signals can cause prohibited design for debug (DfD) overhead, we present an automated trace signal selection methodology that maximizes error detection probability under a given constraint. In addition, we develop a novel trace qualification technique that reduces the storage requirement in trace buffers. The effectiveness of the proposed methodology is verified with large benchmark circuits. © 2010 IEEE.
All Author(s) ListLiu X., Xu Q.
Name of Conference2010 19th IEEE Asian Test Symposium, ATS 2010
Start Date of Conference01/12/2010
End Date of Conference04/12/2010
Place of ConferenceShanghai
Country/Region of ConferenceChina
Detailed descriptionorganized by IEEE,
Pages243 - 248
LanguagesEnglish-United Kingdom

Last updated on 2021-01-03 at 02:13