Fine-grained characterization of process variation in FPGAs
Refereed conference paper presented and published in conference proceedings

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AbstractAs semiconductor manufacturing continues towards reduced feature sizes, yield loss due to process variation becomes increasingly important. To address this issue on FPGA platforms, several variation aware design (VAD) methodologies have been proposed. In this work we present a practical method of process variation characterization (PVC) to facilitate VAD using only intrinsic FPGA resources. The scheme is based on measuring the difference between ring oscillator (RO) delay at different locations within a die, and can be used to perform process variation characterization for LE delays and interconnect delays including direct connection, double wire and hex wires. The difference in loop delays can also be estimated from equations using parameters extracted from primitives and compared with direct measurements. On a Xilinx Spartan-3e device, it was found that the error between the estimated and measured values was on average less than 10%. © 2010 IEEE.
All Author(s) ListYu H., Xu Q., Leong P.H.W.
Name of Conference2010 International Conference on Field-Programmable Technology, FPT'10
Start Date of Conference08/12/2010
End Date of Conference10/12/2010
Place of ConferenceBeijing
Country/Region of ConferenceChina
Detailed descriptionorganized by IEEE,
Pages138 - 145
LanguagesEnglish-United Kingdom

Last updated on 2021-18-02 at 23:47