Structured ASIC: Methodology and comparison
Refereed conference paper presented and published in conference proceedings

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AbstractAs fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully compatible with conventional ASIC design flows and a comparison of area and delay performance with ASICs and FPGAs is given. A prototype structured ASIC implementing an LED-backlit LCD controller was fabricated in a 0.13μm CMOS process. It was verified and power consumption compared with an ASIC design. © 2010 IEEE.
All Author(s) ListHo S.M.H., Yuen S.C.L., Poon H.C., Chau T.C.P., Ai Y.-Q., Leong P.H.W., Choy O.C.S., Pun K.-P.
Name of Conference2010 International Conference on Field-Programmable Technology, FPT'10
Start Date of Conference08/12/2010
End Date of Conference10/12/2010
Place of ConferenceBeijing
Country/Region of ConferenceChina
Detailed descriptionorganized by IEEE,
Pages377 - 380
LanguagesEnglish-United Kingdom

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