Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Refereed conference paper presented and published in conference proceedings


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AbstractClock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthesis. Local clock skew (LCS) is the clock skew between any two sinks with distance less than or equal to a given threshold. It is defined in the ISPD 2010 High Performance Clock Network Synthesis Contest [1], and it is a novel criterion that captures process variation effects on a clock network. In this paper, we propose a hybrid method that creates a mesh upon a tree topology. Total wire and buffer capacitance is minimized under the LCS and slew constraints. In our method, a clock mesh will be built first according to the positions and capacitance of the sinks. A top-level tree is then built to drive the mesh. A blockage-aware routing method is used during the tree construction. Experimental results show our efficiency and the solution generated by our approach can satisfy the LCS constraint of all the benchmarks in the contest [1], with a fair capacitance usage. ©2010 IEEE.
All Author(s) ListXiao L., Xiao Z., Qian Z., Jiang Y., Huang T., Tian H., Young E.F.Y.
Name of Conference2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Start Date of Conference07/11/2010
End Date of Conference11/11/2010
Place of ConferenceSan Jose, CA
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by IEEE,
Year2010
Month12
Day1
Pages458 - 462
ISBN9781424481927
ISSN1092-3152
LanguagesEnglish-United Kingdom

Last updated on 2021-18-02 at 23:46