A 90nm RFID tag's baseband processor with novel PIE decoder and uplink clock generator
Refereed conference paper presented and published in conference proceedings

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AbstractA passive UHF RFID tag's baseband processor design with energy-aware structure is presented in this paper, based on EPC C1G2 protocol. For the consideration of limited availability of power and low-voltage supply, ripple-binary mixed counter and compensated addition are proposed for the PIE decoder. And in the clock generator for tag-to-reader uplink, Galoi linear feedback shift register (LFSR) is utilized to satisfy critical timing requirement. Additionally, double-edge-triggered (DET) flip flop in these two modules helps to improve clock efficiency and reduce the impact of frequency variation at low voltage power supply. Therefore the robustness of the processor is ensured. The whole tag was fabricated in standard 90nm CMOS technology, and in measurement the baseband processor can consume less than 80nW at 0.33V supply. © 2010 IEEE.
All Author(s) ListShi W., Choy C.-S., Guo J., Chan C.F., Leung K.N., Pun K.P.
Name of Conference53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010
Start Date of Conference01/08/2010
End Date of Conference04/08/2010
Place of ConferenceSeattle, WA
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by Circuits and Systems Society,
Pages644 - 647
LanguagesEnglish-United Kingdom

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