A 90nm RFID tag's baseband processor with novel PIE decoder and uplink clock generator
Refereed conference paper presented and published in conference proceedings

替代計量分析
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其它資訊
摘要A passive UHF RFID tag's baseband processor design with energy-aware structure is presented in this paper, based on EPC C1G2 protocol. For the consideration of limited availability of power and low-voltage supply, ripple-binary mixed counter and compensated addition are proposed for the PIE decoder. And in the clock generator for tag-to-reader uplink, Galoi linear feedback shift register (LFSR) is utilized to satisfy critical timing requirement. Additionally, double-edge-triggered (DET) flip flop in these two modules helps to improve clock efficiency and reduce the impact of frequency variation at low voltage power supply. Therefore the robustness of the processor is ensured. The whole tag was fabricated in standard 90nm CMOS technology, and in measurement the baseband processor can consume less than 80nW at 0.33V supply. © 2010 IEEE.
著者Shi W., Choy C.-S., Guo J., Chan C.F., Leung K.N., Pun K.P.
會議名稱53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010
會議開始日01.08.2010
會議完結日04.08.2010
會議地點Seattle, WA
會議國家/地區美國
詳細描述organized by Circuits and Systems Society,
出版年份2010
月份9
日期20
頁次644 - 647
國際標準書號9781424477715
國際標準期刊號1548-3746
語言英式英語

上次更新時間 2021-16-06 於 00:02