ECR: A low complexity generalized error cancellation rewiring scheme
Refereed conference paper presented and published in conference proceedings

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AbstractRewiring is known to be a new class of logic restructuring technique at least equally powerful in flexibility compared to other logic transformation techniques while being wiring-sensitive, a property particularly useful for interconnect based circuit synthesis processes. One of the most mature rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant alternative wire to make an originally irredundant target wire become redundant and thus removable. In this paper, we propose a new Error Cancellation based Rewiring scheme (ECR) which can also do non-RAR based rewiring operations with high efficiency. Based on the notion of error cancellation, we analyze and reformulate the rewiring problem and develop a generalized rewiring scheme being able to detect more rewiring cases which are not obtainable by existing schemes while still maintains low runtime complexity. Comparing with the most recent non-RAR rewiring tool IRRA, the total number of alternative wires found by our approach is about twice while CPU time is just slightly more (26%) upon benchmarks pre-optimized by rewriting of ABC. Copyright 2010 ACM.
All Author(s) ListYang X., Lam T.-K., Wu Y.-L.
Name of Conference47th Design Automation Conference, DAC '10
Start Date of Conference13/06/2010
End Date of Conference18/06/2010
Place of ConferenceAnaheim, CA
Country/Region of ConferenceUnited States of America
Pages511 - 516
LanguagesEnglish-United Kingdom
KeywordsATPG, Error cancellation, Rewire

Last updated on 2021-16-06 at 00:02