Optimization for timing-speculated circuits by redundancy addition and removal
Refereed conference paper presented and published in conference proceedings


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AbstractIntegrated circuits suffer from severe variation effects with technology scaling, making their timing behavior increasingly unpre-dictable. Timing speculation is a promising technique to tackle this problem with the help of online timing error detection and correction mechanisms. In this paper, we propose to use redundancy addition and removal (RAR) technique to optimize timing-speculated circuits. By intentionally removing wires on those frequently-exercised critical paths and replacing them with wires on less critical ones (if possible), the proposed technique is able to greatly reduce the timing error rate of the circuit and improve its overall throughput, as shown in our experimental results on various benchmark circuits. © 2013 IEEE.
All Author(s) ListLiu Y., Ye R., Yuan F., Xu Q.
Name of Conference2013 18th IEEE European Test Symposium, ETS 2013
Start Date of Conference27/05/2013
End Date of Conference30/05/2013
Place of ConferenceAvignon
Country/Region of ConferenceFrance
Detailed descriptionorganized by IEEE,
Year2013
Month9
Day9
ISBN9781467363778
LanguagesEnglish-United Kingdom

Last updated on 2020-20-10 at 00:39