On testing timing-speculative circuits
Refereed conference paper presented and published in conference proceedings


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AbstractBy allowing the occurrence of infrequent timing errors and correcting them online, circuit-level timing speculation is one of the most promising variation-tolerant design techniques. How to effectively test timingspeculative circuits, however, has not been addressed in the literature. This is a challenging problem because conventional scan techniques cannot provide sufficient controllability and observability for such circuits. In this paper, we propose novel techniques to achieve high fault coverage for timing-speculative circuits without incurring high designfor- testability cost. Experimental results on various benchmark circuits demonstrate the effectiveness of the proposed solution. Copyright © 2013 ACM.
All Author(s) ListYuan F., Liu Y., Jone W.-B., Xu Q.
Name of Conference50th Annual Design Automation Conference, DAC 2013
Start Date of Conference29/05/2013
End Date of Conference07/06/2013
Place of ConferenceAustin, TX
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by ACM/IEEE,
Year2013
Month7
Day12
ISBN9781450320719
ISSN0738-100X
LanguagesEnglish-United Kingdom

Last updated on 2020-25-10 at 00:40