VeriTrust: Verification for hardware trust
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
替代計量分析
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其它資訊
摘要Hardware Trojans (HTs) implemented by adversaries serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or Denial of Service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in the literature) at the cost of moderate extra verification time, which is not possible with existing solutions. Copyright © 2013 ACM.
著者Zhang J., Yuan F., Wei L., Sun Z., Xu Q.
會議名稱50th Annual Design Automation Conference, DAC 2013
會議開始日29.05.2013
會議完結日07.06.2013
會議地點Austin, TX
會議國家/地區美國
詳細描述organized by IEEE/ACM,
出版年份2013
月份7
日期12
國際標準書號9781450320719
國際標準期刊號0738-100X
語言英式英語

上次更新時間 2020-13-09 於 00:15