Testing of synchronizers in asynchronous FIFO
Publication in refereed journal

替代計量分析
.

其它資訊
摘要This paper presents a test method for testing two-D-flip-flop synchronizers in an asynchronous first-in-first-out (FIFO) interface. A faulty synchronizer can have different fault behaviors depending on the input application time, the fault location, the fault mechanism, and the applied clock frequency. The proposed test method can apply the input patterns at different time and generate capture clock signals with different frequency regardless of phase-locked loop (PLL) of the design. To implement the proposed test method, channel delay compensator, delayed scan enable signal generator, launch clock generator, and capture clock generator are designed. In addition, a well-designed calibration method is proposed to calibrate all programmable delay elements used in the test circuits. The proposed test method evolves to several test sections to detect all possible faults of the two-D-flip-flop synchronizers in the asynchronous FIFO interface. © 2013 Springer Science+Business Media New York.
著者Kim H.-K., Wang L.-T., Wu Y.-L., Jone W.-B.
期刊名稱Journal of Electronic Testing
詳細描述To ORKTS: Other Keyword:
4. GALS
出版年份2013
月份2
日期14
卷號29
期次1
出版社Kluwer Academic Publishers
出版地Netherlands
頁次49 - 72
國際標準期刊號0923-8174
語言英式英語
關鍵詞Asynchronous FIFO, At-speed delay testing, GALS, Synchronizer

上次更新時間 2020-01-12 於 01:11