On effective through-silicon via repair for 3-D-stacked ICs
Publication in refereed journal


摘要3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3-D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleanness of silicon dies, rendering prior TSV redundancy solutions less effective. Furthermore, existing techniques consume a lot of redundant TSVs that are still costly in the current TSV process. This inefficient TSV redundancy can limit the amount of TSVs that is allowed to use and may even become the obstacle to commercial production. To resolve this problem, we present a novel TSV repair framework, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction. By doing so, the manufacturing yield for 3-D-stacked ICs can be dramatically improved, as demonstrated in our experimental results. © 1982-2012 IEEE.
著者Jiang L., Xu Q., Eklow B.
期刊名稱IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
出版社Institute of Electrical and Electronics Engineers
出版地United States
頁次559 - 571
關鍵詞3-D stacking, redundancy, through-silicon vias (TSV) repair, yield enhancement

上次更新時間 2020-29-11 於 02:32