WRIP: Logic restructuring techniques for wirelength-driven incremental placement
Refereed conference paper presented and published in conference proceedings


摘要This paper presents WRIP-aWirelength-driven Rewiringbased Incremental Placement which effectively reduces wirelength of the optimized placement of industrial large-scale standard cell designs. WRIP uses a powerful logic synthesis technique called logic rewiring which restructures the local circuits while preserving the logic functionality and reduces the wirelength under an accurate estimation of the half perimeter wirelength (HPWL) metric. We integrated WRIP into an industrial EDA tool and tested it upon several real designs with hundreds of thousands of movable objects. Tested on circuits which has been fully optimized by the state-of-the-art industrial placement tool, our experiments showed that on average WRIP reduces wirelength by 2.25% after placement and 2.45% after global routing in HPWL and Steiner WL model respectively. The runtime of WRIP is only about half an hour for the largest tested ASIC circuit. This is the first attempt to fully integrate powerful logic synthesis into industrial placement tools with real-life effectiveness and efficiency. Copyright 2012 ACM.
著者Wei X., Tang W.-C., Wu Y.-L., Sze C., Alpert C.
會議名稱22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
會議地點Salt Lake City, UT
詳細描述To ORKTS: Keyword no.4: Inremental placement
頁次327 - 332
關鍵詞HPWL, Incremental placement, Logic rewiring, Wirelength driven

上次更新時間 2020-16-10 於 01:17