Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Refereed conference paper presented and published in conference proceedings

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AbstractThree-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the "known good die" problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield. In this paper, we survey recent advances in this filed and point out challenges to be resolved in the future. © 2012 IEEE.
All Author(s) ListXu Q., Jiang L., Li H., Eklow B.
Name of Conference17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
Start Date of Conference30/01/2012
End Date of Conference02/02/2012
Place of ConferenceSydney, NSW
Country/Region of ConferenceAustralia
Detailed descriptionorganized by IEEE/ACM,
Pages731 - 737
LanguagesEnglish-United Kingdom

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