Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
替代計量分析
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其它資訊
摘要Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the "known good die" problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield. In this paper, we survey recent advances in this filed and point out challenges to be resolved in the future. © 2012 IEEE.
著者Xu Q., Jiang L., Li H., Eklow B.
會議名稱17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
會議開始日30.01.2012
會議完結日02.02.2012
會議地點Sydney, NSW
會議國家/地區澳大利亞
詳細描述organized by IEEE/ACM,
出版年份2012
月份4
日期26
頁次731 - 737
國際標準書號9781467307727
語言英式英語

上次更新時間 2020-14-10 於 01:51