Postgrid clock routing for high performance microprocessor designs
Refereed conference paper presented and published in conference proceedings

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其它資訊
摘要Designing a high-quality clock network is very important in very large-scale integrated designs today, as it is the clock network that synchronizes all the elements of a chip, and it is also a major source of power dissipation of a system. Early study by Pham in 2006 shows that about 18.1% of the total clock capacitance was due to this postgrid clock routing (i.e., lower mesh wires plus clock twig wires). In this paper, we proposed a partition-based path expansion algorithm to solve this postgrid clock routing problem effectively. Experimental results on industrial test cases show that our algorithm can improve over the latest work by Shelar on this problem significantly by reducing the wire capacitance by 24.6% and the wirelength by 23.6%. © 2006 IEEE.
著者Tian H., Tang W.-C., Young E.F.Y., Sze C.N.
出版年份2012
月份2
日期1
卷號31
期次2
出版社Institute of Electrical and Electronics Engineers
出版地United States
頁次255 - 259
國際標準期刊號0278-0070
語言英式英語
關鍵詞Clock routing, microprocessor design, postgrid

上次更新時間 2020-28-10 於 02:41