Modeling and tools for power supply variations analysis in networks-on-chip
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AbstractPower supply integrity has become a critical concern with the rapid shrinking feature size and the ever increasing power consumption in nanometre scale integration. In particular, on-chip communication in platforms such as networks-on-chip (NoC) dictates the power dissipation and overall system performance in multicore systems and embedded computing architectures. These architectures require a dedicated tool for analyzing the power supply noise which must embed distinctive communication characteristics and spatial parameters. In this paper, we present a tool dedicated to determining the on-chip (VDD) drops due to communication workload in NoCs. This tool integrates a fast power grid model, an NoC simulator, an on-chip link model, and a microarchitectural power model for router. The model has been rigorously verified using SPICE simulations. The proposed model and tools are further exemplified through analyzing the impact of power supply noise for NoC links. Statistical timing analysis of NoC links in the presence of power supply noise was performed to evaluate the bit error rates (BERs). This work would enable better understanding of the tradeoffs existing in the design of NoCs, and the induced power supply noise due to on-chip communication. This understanding is crucial for the analysis of the quality of service (QoS) of communication fabrics in NoCs at the early design stages. © 1968-2012 IEEE.
All Author(s) ListDahir N.S., Mak T., Xia F., Yakovlev A.
Journal nameIEEE Transactions on Computers
Year2014
Month1
Day1
Volume Number63
Issue Number3
PublisherInstitute of Electrical and Electronics Engineers
Place of PublicationUnited States
Pages679 - 690
ISSN0018-9340
eISSN1557-9956
LanguagesEnglish-United Kingdom
Keywordsbit error rate, Networks-on-chip, on-chip routing, power grid granularity, power grid simulation, power supply noise, probability of error, timing analysis

Last updated on 2020-20-10 at 03:20