Eliminating synchronization latency using sequenced latching
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AbstractModern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. We propose a speculative method that hides synchronization latency by overlapping it with computation cycles. We verify the correctness of our approach through a field programmable gate array implementation and apply it to a number of synthesized benchmarks. Synthesis results reveal that our approach achieves average savings of 135% and 204% in area costs and nearly 100% in power costs compared to two similar speculative techniques. © 1993-2012 IEEE.
All Author(s) ListTarawneh G., Yakovlev A., Mak T.
Journal nameIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year2014
Month2
Day1
Volume Number22
Issue Number2
PublisherInstitute of Electrical and Electronics Engineers
Place of PublicationUnited States
Pages408 - 419
ISSN1063-8210
eISSN1557-9999
LanguagesEnglish-United Kingdom
KeywordsDuplication, latency, metastability, speculation, synchronization

Last updated on 2020-17-10 at 02:43