On the premises and prospects of timing speculation
Refereed conference paper presented and published in conference proceedings


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AbstractTiming speculation (TS), being able to detect and correct circuit timing errors at runtime, is a promising alternative solution to mitigate the ever-increasing variation effects in nanometer circuits. The potential energy-efficiency improvement, however, is limited by the circuit 'timing wall', a critical operating point caused by conventional circuit optimization techniques (e.g., gate sizing). With a given circuit netlist, we study the bound of the potential benefits provided by TS techniques in this work, which facilitate designers to decide whether it worths the effort to implement a timing-speculative circuit. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed methodology.
All Author(s) ListYe R., Yuan F., Zhang J., Xu Q.
Name of Conference2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Start Date of Conference09/03/2015
End Date of Conference13/03/2015
Place of ConferenceGrenoble
Country/Region of ConferenceFrance
Detailed descriptionorganized by IEEE/ACM,
Year2015
Month1
Day1
Volume Number2015-April
Pages605 - 608
ISBN9783981537048
ISSN1530-1591
LanguagesEnglish-United Kingdom

Last updated on 2020-05-08 at 02:57