A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration
Publication in refereed journal

香港中文大學研究人員
替代計量分析
.

其它資訊
摘要This paper presents a high resolution time-to-digital converter (TDC) architecture, which combines the advantages of sub-ranging and Vernier delay line TDCs. In the proposed TDC, the time input is converted to a digital code in a coarse-fine manner by two stages of parallel delay lines. Both stages have coarse (but slightly different) time resolutions. The effective fine resolution of the second stage is achieved by making it work with the first stage in a Vernier manner. To alleviate the linearity problem caused by random variations of the delays of the delay elements, a foreground DNL calibration technique is proposed. A proof-of-the-concept Vernier sub-ranging (3+3)-bit TDC was designed and fabricated in a 0.13-�gm CMOS process. It demonstrates a resolution of 5 ps, a DNL of 0.6 LSB and a single-shot precision of 0.4 LSB at a conversion rate of 10 Msps while consuming 1.15 mW from 1.2 V at a conversion rate of 20 Msps.
著者Ko C.-T., Pun K.-P., Gothenberg A.
期刊名稱Microelectronics Journal
出版年份2015
月份12
日期1
卷號46
期次12
出版社Elsevier BV
出版地Netherlands
頁次1469 - 1480
國際標準期刊號0026-2692
語言英式英語
關鍵詞All-digital phase-lock loop, Digital calibration, Time-to-digital converter, Vernier delay line

上次更新時間 2020-01-12 於 00:56