A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration
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AbstractThis paper presents a high resolution time-to-digital converter (TDC) architecture, which combines the advantages of sub-ranging and Vernier delay line TDCs. In the proposed TDC, the time input is converted to a digital code in a coarse-fine manner by two stages of parallel delay lines. Both stages have coarse (but slightly different) time resolutions. The effective fine resolution of the second stage is achieved by making it work with the first stage in a Vernier manner. To alleviate the linearity problem caused by random variations of the delays of the delay elements, a foreground DNL calibration technique is proposed. A proof-of-the-concept Vernier sub-ranging (3+3)-bit TDC was designed and fabricated in a 0.13-�gm CMOS process. It demonstrates a resolution of 5 ps, a DNL of 0.6 LSB and a single-shot precision of 0.4 LSB at a conversion rate of 10 Msps while consuming 1.15 mW from 1.2 V at a conversion rate of 20 Msps.
All Author(s) ListKo C.-T., Pun K.-P., Gothenberg A.
Journal nameMicroelectronics Journal
Volume Number46
Issue Number12
PublisherElsevier BV
Place of PublicationNetherlands
Pages1469 - 1480
LanguagesEnglish-United Kingdom
KeywordsAll-digital phase-lock loop, Digital calibration, Time-to-digital converter, Vernier delay line

Last updated on 2021-10-09 at 23:50