A high-speed pipeline architecture of squarer-accumulator (SQAC)
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香港中文大學研究人員

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摘要

This paper presents a high-speed pipeline architecture
for squarer-accumulator (SQAC). The proposed design integrates squarer into multiplier-accumulator
(MAC), producing the SQAC, which is utilized widely in signal processing field.
The proposed architecture takes advantage of carry-save technique in the
accumulation, and utilizes a novel feedback scheme. These ideas could also be
applied to improve the performance of MAC. In estimation, the proposal is synthesized
with TSMC CMOS libraries of 180nm, 130nm, 90nm and 65nm technology. Simulation results
show that our proposed architecture provides almost 50% improvement compared
with previous realizations in terms of time and area cost.

出版社接受日期29.08.2016
著者WANG J, XU L, WANG H, CHOY C
會議名稱IEEE TENCON 2016
會議開始日22.11.2016
會議完結日25.12.2016
會議地點The Marina Bay Sands Convention Centre, Singapore
會議國家/地區新加坡
出版年份2016
語言英式英語

上次更新時間 2018-21-01 於 21:38