A high-speed pipeline architecture of squarer-accumulator (SQAC)
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Officially Accepted for Publication


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Abstract

This paper presents a high-speed pipeline architecture
for squarer-accumulator (SQAC). The proposed design integrates squarer into multiplier-accumulator
(MAC), producing the SQAC, which is utilized widely in signal processing field.
The proposed architecture takes advantage of carry-save technique in the
accumulation, and utilizes a novel feedback scheme. These ideas could also be
applied to improve the performance of MAC. In estimation, the proposal is synthesized
with TSMC CMOS libraries of 180nm, 130nm, 90nm and 65nm technology. Simulation results
show that our proposed architecture provides almost 50% improvement compared
with previous realizations in terms of time and area cost.

Acceptance Date29/08/2016
All Author(s) ListWANG J, XU L, WANG H, CHOY C
Name of ConferenceIEEE TENCON 2016
Start Date of Conference22/11/2016
End Date of Conference25/12/2016
Place of ConferenceThe Marina Bay Sands Convention Centre, Singapore
Country/Region of ConferenceSingapore
Year2016
LanguagesEnglish-United Kingdom

Last updated on 2018-21-01 at 21:38