A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs
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AbstractStatic random access memories (SRAMs) built on carbon nanotube field effect transistors (CNFETs) are promising alternatives to conventional CMOS-based SRAMs, due to their advantages in terms of power consumption and noise immunity. However, the nonideal carbon nanotube (CNT) fabrication process generates metallic-CNTs (m-CNTs) along with semiconductor-CNTs, leading to correlated faulty cells along the growth direction of the m-CNTs. In this paper, we propose a novel low-cost test solution to detect such faults. Instead of using conventional March test to test each and every SRAM cell, we selectively test certain SRAM cells and judiciously skip testing other SRAM cells between the selected cells. To ensure high fault coverage, we propose three jump test algorithms for different CNFET-SRAM layouts. Moreover, we model m-CNT-induced SRAM faults and characterize their distribution in the SRAM array. Experimental results show that the proposed solutions are able to achieve high fault coverage with low test cost.
All Author(s) ListLi TJ, Xie F, Liang XY, Xu Q, Chakrabarty K, Jing NF, Jiang L
Journal nameIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume Number35
Issue Number7
Pages1192 - 1205
LanguagesEnglish-United Kingdom
KeywordsCarbon nanotubes (CNTs); integrated circuit testing; static random access memory (SRAM) cells
Web of Science Subject CategoriesComputer Science; Computer Science, Hardware & Architecture; Computer Science, Interdisciplinary Applications; Engineering; Engineering, Electrical & Electronic

Last updated on 2021-12-01 at 00:54