TILA: Timing-Driven Incremental Layer Assignment
Refereed conference paper presented and published in conference proceedings

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AbstractAs VLSI technology scales to deep submicron and beyond, interconnect delay greatly limits the circuit performance. The traditional 2D global routing and subsequent net by net assignment of available empty tracks on various layers lacks a global view for timing optimization. To overcome the limitation, this paper presents a timing driven incremental layer assignment tool, TILA, to reassign layers among routing segments of critical nets and non-critical nets. Lagrangian relaxation techniques are proposed to iteratively provide consistent layer/via assignments. Modeling via min-cost flow for layer shuffling avoids using integer programming and yet guarantees integer solutions via uni-modular property of the inherent model. In addition, multiprocessing of K x K partitions of the whole chip provides run time speed up. Certain parameters introduced in the models provide trade-off between timing optimization and via count. Experimental results in both ISPD'08 and industry benchmark suites demonstrate the effectiveness of the proposed incremental algorithms.
All Author(s) ListYu B, Liu DR, Chowdhury S, Pan DZ
Name of Conference34th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Start Date of Conference02/11/2015
End Date of Conference06/11/2015
Place of ConferenceAustin
Country/Region of ConferenceUnited States of America
Detailed descriptionorganized by IEEE/ACM,
Pages110 - 117
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesComputer Science; Computer Science, Theory & Methods; Engineering; Engineering, Electrical & Electronic

Last updated on 2020-05-08 at 05:53