Wafer-Level Wet Etching of High-Aspect-Ratio Through Silicon Vias (TSVs) with High Uniformity and Low Cost for Silicon Interposers with High-Density Interconnect of 3D Packaging
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
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摘要Silicon (Si) interposers have received an increasing amount of attention in microelectronic packaging industry due to its potential application in the emerging 2.5D system integration. One of the key steps in the fabrication flow of Si interposer is the formation of through silicon vias (TSVs), which enable the vertical communication of chips attached on either side of the interposer. Current method for TSVs formation suffers from high cost and low throughput. In this paper, we report successful TSVs formation by a novel wet chemical method, which is named as metal-assisted chemical etching (MaCE). In a typical experiment, fast etching of TSVs with 30 mu m in diameter, 80 mu m in pitch size, less than 50 nm in sidewall roughness and maximum depth of 330 mu m on standard Si substrates is demonstrated. Effect of etching time, temperature of the etchant and application of external electric bias are discussed by comparative study. Uniformity of the TSVs array by MaCE is investigated. The results clearly demonstrate that MaCE is a promising method for TSVs formation on Si interposers with cost-efficiency and high throughput in large-scale manufacturing.
著者Li LL, Wu JL, Wong CP
會議名稱IEEE 65th Electronic Components and Technology Conference (ECTC)
會議開始日26.05.2015
會議完結日29.05.2015
會議地點San Diego
會議國家/地區美國
期刊名稱2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)
會議論文集題名2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)
出版作品名稱2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)
出版年份2015
月份1
日期1
頁次1417 - 1422
國際標準期刊號0569-5503
語言英式英語
Web of Science 學科類別Computer Science, Theory & Methods;Engineering, Electrical & Electronic;Computer Science;Engineering

上次更新時間 2020-08-08 於 02:40