A bit-serial implementation of the International Data Encryption Algorithm IDEA
Refereed conference paper presented and published in conference proceedings

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AbstractA high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication module 2(16) + 1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500Mb/sec. With a XCV1000-6 device, the estimated performance is 2Gb/sec, three orders of magnitude faster than a software implementation on a 450MHz Intel Pentium II. This design is suitable for applications an on-line encryption for high-speed networks.
All Author(s) ListLeong MP, Cheung OYH, Tsoi KH, Leong PHW
Name of ConferenceIEEE Symposium on Field-Programmable Custom Computing Machines
Start Date of Conference17/04/2000
End Date of Conference19/04/2000
Place of ConferenceNAPA VALLEY
Country/Region of ConferenceUnited States of America
Year2000
Month1
Day1
PublisherIEEE COMPUTER SOC
Pages122 - 131
ISBN0-7695-0871-5
LanguagesEnglish-United Kingdom
Web of Science Subject CategoriesComputer Science; Computer Science, Hardware & Architecture; Computer Science, Theory & Methods

Last updated on 2020-22-05 at 00:05