A bit-serial implementation of the International Data Encryption Algorithm IDEA
Refereed conference paper presented and published in conference proceedings

香港中文大學研究人員
作者已離職


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其它資訊
摘要A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication module 2(16) + 1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500Mb/sec. With a XCV1000-6 device, the estimated performance is 2Gb/sec, three orders of magnitude faster than a software implementation on a 450MHz Intel Pentium II. This design is suitable for applications an on-line encryption for high-speed networks.
著者Leong MP, Cheung OYH, Tsoi KH, Leong PHW
會議名稱IEEE Symposium on Field-Programmable Custom Computing Machines
會議開始日17.04.2000
會議完結日19.04.2000
會議地點NAPA VALLEY
會議國家/地區美國
出版年份2000
月份1
日期1
出版社IEEE COMPUTER SOC
頁次122 - 131
國際標準書號0-7695-0871-5
語言英式英語
Web of Science 學科類別Computer Science; Computer Science, Hardware & Architecture; Computer Science, Theory & Methods

上次更新時間 2021-09-10 於 00:28